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T89C51CC02芯片二次解密与技术分析

时间:2011-04-11 08:43:53

芯片解密过程中,对芯片内部结构及其加解密特征进行技术分析是解密工程师的一项必修课,因为只有充分理解芯片内部结构原理等技术信息,工程师才能准确进行方案开发,确定最可靠、成功率最高的解密方案,最大限度确保解密项目的安全可靠。
T89C51CC02芯片技术特点:
·80C51 Core Architecture
·256 Bytes of On-chip RAM
·256 Bytes of On-chip XRAM
·16K Bytes of On-chip Flash Memory
– Data Retention: 10 Years at 85°C
– Erase/Write Cycle: 100K
·Boot Code Section with Independent Lock Bits
·2K Bytes of On-chip Flash for Bootloader
·In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability
·2K Bytes of On-chip EEPROM
– Erase/Write Cycle: 100K
·14-sources 4-level Interrupts
·Three 16-bit Timers/Counters
·Full Duplex UART Compatible 80C51
·Maximum Crystal Frequency 40 MHz. In X2 Mode, 20 MHz (CPU Core, 40 MHz)
·Three or Four Ports: 16 or 20 Digital I/O Lines
·Two-channel 16-bit PCA
– PWM (8-bit)
– High-speed Output
– Timer and Edge Capture
·Double Data Pointer
·21-bit Watchdog Timer (7 Programmable bits)
·A 10-bit Resolution Analog-to-Digital Converter (ADC) with 8 Multiplexed Inputs
·Full CAN Controller
– Fully Compliant with CAN rev.# 2.0A and 2.0B
– Optimized Structure for Communication Management (Via SFR)
– 4 Independent Message Objects
-Each Message Object Programmable on Transmission or Reception
-Individual Tag and Mask Filters up to 29-bit Identifier/Channel
-8-byte Cyclic Data Register (FIFO)/Message Object
-16-bit Status and Control Register/Message Object
-16-bit Time-Stamping Register/Message Object
-CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message Object
-Access to Message Object Control and Data Registers Via SFR
-Programmable Reception Buffer Length up to 4 Message Objects
-Priority Management of Reception of Hits on Several Message Objects Simultaneously (Basic CAN Feature)
-Priority Management for Transmission
-Message Object Overrun Interrupt
– Supports
-Time Triggered Communication
-Autobaud and Listening Mode
-Programmable Automatic Reply Mode
·1-Mbit/s Maximum Transfer Rate at 8 MHz(1)
Crystal Frequency In X2 Mode
·Readable Error Counters
·Programmable Link to On-chip Timer for Time Stamping and Network Synchronization
·Independent Baud Rate Prescaler
·Data, Remote, Error and Overload Frame Handling
·Power-saving Modes
–Idle Mode
– Power-down Mode
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