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EPM3256A芯片技术破解与研究

时间:2011-03-31 08:58:01

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EPM3256A芯片简介:
High- performance, low- cost CMOS EEPROM- based programmab architecture
logic devices (PLDs) built on a MAX 3.3-V in-system programmability (ISP) through the built IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
- ISP circuitry compliant with IEEE Std. 153 Built- in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1-1990 Enhanced ISP features:
- Enhanced ISP algorithm for faster programmin
- ISP_Done bit to ensure complete programmin
- Pull-up resistor on I/O pins during in- system programmi High- density PLDs ranging from 600 to 10,000 usable gates 4.5- ns pin- to- pin logic delays with counter frequencies of up 227.3MHz
TM MultiVolt  I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0- V, 3.3- V, and 2.5- V log
levels Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), plastic J- lead chip carrier TM packages
(PLCC), and FineLine BGA Hot- socketing suppor Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance
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