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EPM240芯片二次开发与解密

时间:2011-03-29 09:12:18

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EPM240芯片简介
All MAX  II devices provide Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry that complies with the IEEE Std. 1149.1-2001 specification. JTAG boundary-scan testing can only be performed at any  and all V  banks have been fully powered and a time after V
CCINT CCIO amount of time has passed. MAX II devices can also use the JTAG CONFIG port for in-system programming together with either the Quartus TM software or hardware using Programming Object Files (.pof), Jam Standard Test and Programming Language (STAPL) Files (.jam) or Jam Byte-Code Files (.jbc).
The JTAG pins support 1.5-V, 1.8-V, 2.5-V, or 3.3-V I/O standards. The of the supported voltage level and standard is determined by the V
CCIO bank where it resides. The dedicated JTAG pins reside in Bank 1 of all MAX II devices.
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